MII, RMII, GMII, and RGMII are all standards that define the interface between a MAC (Media Access Controller, typically part of a processor or switch) and a PHY (Physical Interface Transceiver, the chip that actually drives the Ethernet cable).
Their core purpose is the same: to move data between the MAC and PHY. The key differences lie in speed, number of signals (pin count), and clocking strategies.
Here is a summary table followed by a detailed explanation of each standard.
Comparison Table at a Glance
| Feature | MII (Media Independent Interface) | RMII (Reduced MII) | GMII (Gigabit MII) | RGMII (Reduced GMII) |
|---|---|---|---|---|
| Primary Speed | 10/100 Mbps | 10/100 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
| Data Path Width | 4 bits (nibble) | 2 bits | 8 bits (byte) | 4 bits (nibble) |
| TX/RX Data Lines | 4 TXD, 4 RXD (8 total) | 2 TXD, 2 RXD (4 total) | 8 TXD, 8 RXD (16 total) | 4 TXD, 4 RXD (8 total) |
| Clock Signals | TX_CLK, RX_CLK (2 total) | REF_CLK (1 clock for both TX & RX) | GTX_CLK, RX_CLK (2 total) | TX_CLK, RX_CLK (DDR - Double Data Rate) |
| Total Pin Count (approx.) | ~18 | ~8 | ~24 | ~12 |
| Key Advantage | Original standard, simple | Low pin count, cost-effective for 100Mbps | Enables Gigabit Ethernet | Low pin count + Gigabit speed |
| Key Disadvantage | High pin count for the speed | Requires a precise 50 MHz reference clock | Very high pin count (impractical for many designs) | Requires DDR timing, more sensitive to layout |
| Typical Clock Freq. | 25 MHz (10Mbps), 2.5 MHz (100Mbps) | 50 MHz | 125 MHz (for 1000Mbps) | 125 MHz (but DDR, so 250 Mbps per pin) |
Detailed Explanation of Each Standard
1. MII (Media Independent Interface)
The original standard for 10 and 100 Mbps (10/100) Ethernet.
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Data Path: It uses a 4-bit (nibble) wide data bus for both transmission (TXD[3:0]) and reception (RXD[3:0]).
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Clocking: It has two separate clocks:
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TX_CLK: Provided by the PHY to the MAC, synchronized to the transmit data. (25 MHz for 100Mbps, 2.5 MHz for 10Mbps).
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RX_CLK: Provided by the PHY to the MAC, synchronized to the receive data. (25 MHz for 100Mbps, 2.5 MHz for 10Mbps).
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Why it was reduced: With 8 data lines and 2 clock lines (plus control signals), the pin count was considered high, especially for cost-sensitive or space-constrained embedded systems. This led to the development of RMII.
2. RMII (Reduced Media Independent Interface)
A streamlined version of MII for 10/100 Mbps, specifically designed to halve the pin count.
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Data Path: It uses a 2-bit wide data bus (TXD[1:0], RXD[1:0]).
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Clocking: This is the biggest change. RMII uses a single, common 50 MHz REF_CLK. This clock can be sourced from the MAC or an external oscillator, but it must be very precise.
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The MAC and PHY both use this same 50 MHz clock to sample the 2-bit data. To maintain the 100 Mbps data rate with only 2 bits, the clock frequency is doubled to 50 MHz (2 bits * 50 MHz = 100 Mbps).
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Advantage: Significantly lower pin count, making it cheaper and easier to route on a PCB.
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Disadvantage: Relies on a single, high-quality clock. Any imperfection in the clock affects both transmit and receive paths.
3. GMII (Gigabit Media Independent Interface)
The natural extension of MII to support 1000 Mbps (Gigabit) Ethernet.
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Data Path: To handle the higher data rate, it uses an 8-bit (byte) wide data bus (TXD[7:0], RXD[7:0]).
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Clocking:
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GTX_CLK: A 125 MHz clock provided by the MAC to the PHY for transmit data.
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RX_CLK: A 125 MHz clock provided by the PHY to the MAC for receive data.
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(8 bits * 125 MHz = 1000 Mbps).
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Why it was reduced: The pin count became even more impractical (~24 signals just for data and clock). While defined in the standard, GMII is rarely used in practice directly on PCB traces due to this high pin count. It's more common as an internal interface within FPGAs or ASICs. This led to the widely adopted RGMII.
4. RGMII (Reduced Gigabit Media Independent Interface)
The most common standard for Gigabit Ethernet in embedded systems, achieving a 50% reduction in pin count compared to GMII.
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Data Path: It uses a 4-bit (nibble) wide data bus, just like the original MII, but for Gigabit speeds.
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Clocking (The Key Innovation): RGMII uses DDR (Double Data Rate) clocking.
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It has separate TX_CLK and RX_CLK, both running at 125 MHz.
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However, data is transferred on both the rising and falling edges of the clock. This means 4 bits are transferred per clock cycle at 125 MHz, achieving the required 500 Mbps per direction (4 bits * 125 MHz * 2 (DDR) = 1000 Mbps).
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Timing Challenge: Because of DDR, the timing between the clock and data signals is very tight. The standard defines two modes to help with this:
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Default: Data is aligned with the clock edges. Requires very careful PCB trace length matching.
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RGMII with Internal Delay: The PHY and/or MAC internally delay the clock by a few nanoseconds, making PCB layout much easier. This is the modern and highly recommended approach.
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Advantage: The perfect balance, providing Gigabit speed with a manageable pin count.
Summary Analogy
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MII: A 4-lane highway with a separate speed limit sign (clock) for each direction. Effective, but uses a lot of space (pins).
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RMII: A 2-lane highway with a single, synchronized traffic light (REF_CLK) controlling both directions. Saves space but requires the light to be perfectly timed.
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GMII: An 8-lane superhighway for Gigabit traffic. Very wide and fast, but takes up a massive amount of space (pins), making it expensive to build.
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RGMII: A 4-lane superhighway where cars (data bits) travel two-abreast in each lane (DDR clocking). It achieves the same capacity as the 8-lane highway but uses half the space, making it the most efficient and popular design for modern Gigabit connections.
