Here are four proven ways to bring a 24 V industrial “logic” signal down to safe, clean 3.3 V for an MCU/FPGA. Pick the path that fits your noise/isolation/speed needs.
1) Simple divider (+ Schmitt clean-up) — non-isolated, cheapest
When to use: Short wires, benign EMI, up to a few-100 kHz, no isolation needed.
Schematic (text):
24 V_in ── R1 ──●── to MCU (or Schmitt buffer @3.3 V)
│
C1
│
R2
│
GND
Suggested values (robust for 24 V ±25% and transients):
-
R1 = 287 kΩ (1%)
-
R2 = 31.6 kΩ (1%) → Divider ≈ 0.099 → 30 V → ~2.98 V; 24 V → ~2.38 V
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C1 = 10 nF (forms ~0.28 ms RC with R_th ≈ 28.5 kΩ) for a little debounce/noise filtering
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Optional front-end surge clamp: 33 V TVS diode across 24 V_in–GND (e.g., SMBJ33A class)
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Optional clean-up: a 3.3 V Schmitt-trigger buffer (e.g., “1G17/1G14” family powered at 3.3 V) between the node and your MCU pin
Why it works:
At 30 V worst case you still stay < 3.3 V. The RC and Schmitt kill slow/noisy edges. Divider current is ~75 µA @ 24 V, so it runs cool.
2) NPN “open-collector” translator — non-isolated, noise-tolerant, inverts
When to use: Longish cables, dirty environments, want a solid logic low at the MCU. (Logic is inverted; flip in software if needed.)
Schematic (text):
24 V_in ── Rb ──►|B NPN
E── GND
MCU_in ──(10 k pull-up to 3.3 V)──●── C
(Optionally 10–100 nF from MCU_in to GND)
Suggested values:
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Rb = 100 kΩ (limits base current ≈ 0.23 mA @ 24 V)
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Pull-up = 10 kΩ to 3.3 V (collector current ≈ 0.33 mA when ON)
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Base-to-GND 100 kΩ (ensures hard-OFF when input floats)
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Optional 5.1 V zener from base to emitter for extra surge toughness
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Optional 33 V TVS on the 24 V line
Behavior:
24 V present → transistor saturates → MCU_in = LOW.
0 V → transistor off → MCU_in pulled HIGH (3.3 V).
Very robust against line trash; parts are commodity.
3) Opto-isolated 24 V input — safest for ground loops/EMC
When to use: Different ground domains, long cables leaving the enclosure, industrial sensors (PNP/NPN), compliance/EMC.
Schematic (text):
24 V_in ── R_in ──►| LED (opto) |◄── Diode (reverse protection) ── GND_iso_in
Opto transistor side: Collector ── 10 k → 3.3 V, Emitter → GND_logic, Node → MCU_in
(Optionally 10–100 nF from Node to GND_logic)
Suggested values:
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R_in = 12 kΩ, 0.25 W → ~2.0 mA @ 24 V; ~2.4 mA @ 30 V
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Pull-up 10 kΩ to 3.3 V on the transistor collector
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Optional 33 V TVS on the 24 V line; optional input RC if you want debounce
Notes:
This also inverts (LED on → MCU_in LOW). Choose an opto with adequate CTR; for very low LED current or high speed, pick a logic-gate opto or a digital isolator (ADuM/Si86xx) instead.
4) Comparator with hysteresis — clean thresholds, adjustable, non-isolated
When to use: You want a defined turn-ON/OFF voltage and debounced edges (e.g., treat > 12 V as “1”, < 8 V as “0”).
How:
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First scale 24 V with a divider (same as #1: 287 k / 31.6 k → ~×0.1).
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Feed that into the non-inverting input of a 3.3 V comparator (or your MCU’s internal comparator).
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Make Vref = 1.65 V (10 k/10 k divider from 3.3 V).
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Add positive feedback (≈1 MΩ from comparator output to + input) to create ~0.2–0.4 V hysteresis at the comparator pin → ~2–4 V hysteresis referred to the 24 V line.
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Optional RC at the scaled node for extra filtering.
Result: Crisp, bounce-free logic, non-inverting, with tunable thresholds.
Quick chooser
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Cheapest / simplest, OK noise: #1 Divider + (optional) Schmitt
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No-nonsense robustness (inverted): #2 NPN
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Galvanic isolation / industrial wiring: #3 Opto (or digital isolator)
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Precise thresholds / hysteresis: #4 Comparator
Industrial tips (don’t skip these)
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Transients: 24 V rails can hit 30–36 V and see spikes. Add a TVS and keep the divider sized so Vnode < 3.3 V at the worst-case steady input.
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EMI & ESD: Place the TVS and series parts right at the connector; short return to chassis/ground.
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RC filter: 1–10 nF at the logic node is plenty for contact bounce and cable hash; increase for slower signals.
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Sensor types:
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PNP (sourcing) sensor: output → your input; your input’s return → sensor 0 V.
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NPN (sinking) sensor: tie your input through a pull-up (or use circuits #2/#3).
-
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Inversion: #2 and #3 invert. Flip logic in firmware or add a second transistor/buffer if you need non-inverting.
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Analog (if you meant analog scaling): Use a precision divider + op-amp buffer (or an instrumentation amplifier) and protect with TVS + input resistors; don’t feed raw 24 V into a 3.3 V ADC pin.
Ready-to-copy BOMs
A. Divider + Schmitt (non-isolated, non-inverting)
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R1 287 kΩ 1%
-
R2 31.6 kΩ 1%
-
C1 10 nF X7R
-
Schmitt buffer, 3.3 V, 1-gate (optional)
B. Opto (isolated, inverting)
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R_in 12 kΩ 0.25 W
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Diode 1N4148 (reverse across LED)
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Optocoupler (generic phototransistor type with decent CTR, or logic-gate opto for speed)
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Pull-up 10 kΩ to 3.3 V
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RC 10 nF (optional)
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TVS 33 V at the 24 V side (optional but recommended)
